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CHAPTER 20 USART
reception or transmission clock
(SCES = 0, CCO = 1):
reception or transmission clock
(SCES = 1, CCO = 1):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
●
Error detection:
If no start/stop bits is selected (ECCRn: SSM = 0) only overrun errors are detected.
●
Communication:
For initialization of the synchronous mode, following settings have to be done:
Baud rate generator registers (BGRn):
Set the desired reload value for the dedicated baud rate reload counter.
Serial mode control register (SMRn):
MD1, MD0: "10
SCKE: "1" for the dedicated Baud Rate Reload Counter
SOE: "1" for transmission and reception
Serial control register (SCRn):
RXE, TXE: set both of these flags to "0"
A/D: no Address/Data selection - don't care
CL: automatically fixed to 8-bit data - don't care
CRE: "1" to clear receive error flags.
-- when SSM=0 (default):
PEN, P, SBL: don't care
-- when SSM=1:
PEN: "1" if parity bit is added/detected, "0" if not
P: "0" for even parity, "1" odd parity
SBL: "1" for 2 stop bits, "0" for 1 stop bit.
Serial status register (SSRn):
BDS: "0" for LSB first, "1" for MSB first
RIE: "1" if interrupts are used; "0" receive interrupts are disabled.
TIE: "1" if interrupts are used; "0" transmission interrupts are disabled.
Extended communication control register (ECCRn):
SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (special)
518
Figure 20.7-5 Continuous clock output in mode 2
" (Mode 2)
B
"0" for external clock input
"0" for reception only
MB96300 Super Series Hardware Manual
ST
SP
data frame
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