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CHAPTER 20 USART
20.7.2
Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for USART operation mode 2 (normal
mode).
■ Operation in synchronous mode (operation mode 2)
●
Transfer data format
In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended
Communication Control Register (ECCRn) is 0. The figure below illustrates the data format during a
transmission in the synchronous operation mode.
Reception or transfer data
(ECCRn:SSM=0, SCRn:PEN=0)
Reception or transfer data
(ECCRn:SSM=1, SCRn:PEN=0)
Reception or transfer data
(ECCRn:SSM=1, SCRn:PEN=1)
●
Clock inversion and start/stop bits in mode 2
If the SCES bit of the Extended Status/Control Register (ESCRn) is set the serial clock is inverted. Therefore
in slave mode USART samples the data bits at the falling edge of the received serial clock. Note, that in
master mode if SCES is set the clock signal's mark level is "0". If the SSM bit of the Extended
Communication Control Register (ECCRn) is set the data format gets additional start and stop bits like in
asynchronous mode.
516
Figure 20.7-2 Transfer data format (operation mode 2)
D0
D1
ST
D0
ST
D0
* only if SBL bit of SCRn is set to
ST: Start Bit
SP: Stop Bit
P : Parity Bit
MB96300 Super Series Hardware Manual
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
1
*
SP SP
*
P
SP SP
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