CHAPTER 20 USART
Serial
clock
Serial
Input
(LIN bus)
LBD
Internal
ICU
Signal
LIN Synch Break Detection Interrupt and Flags
522
Figure 20.7-7 USART behavior as slave in LIN mode
Synch break
(e. g. 14 Tbit)
MB96300 Super Series Hardware Manual
LBR cleared
by CPU
Synch field