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CHAPTER 8 RESETS AND STARTUP
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Activation of the Clock stop detection reset
The Clock stop detection reset is enabled by setting the RCR: CSDRE bit to "1".
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Generating a Clock stop detection reset
A Clock stop detection reset is generated in the following cases. The Clock Stop Detection Reset Enable bit
CSDRE must always be set to "1" (reset enabled).
• When a missing Main clock is detected while the Main clock is stabilized (CKMR:MCM = '1') and the
Main or PLL clock is used for the System clocks CLKS1 or CLKS2 or the Watchdog timer. The MCRST
(Main clock stop detection Reset cause) bit is set and a reset is generated.
• When a missing Sub clock is detected while the Sub clock is stabilized (CKMR:SCM = '1') and used for
the System clocks CLKS1 or CLKS2 or the Watchdog timer. The SCRST (Sub clock stop detection Reset
cause) bit is set and a reset is generated.
• When a "0" is written to the CKSR: RCE bit (disable RC clock). Both clock stop detection reset cause bits
are set and a reset is generated. Do not disable the RC clock as long as the Clock stop detection reset is
enabled.
Note:
A clock stop detection reset is generated only when the failing clock is used for the System clock 1 or 2
or for the Watchdog timer. In case a failing clock is only used by a resource (for example Main clock
timer or Sub clock timer) while the System clocks are set to another clock, no reset is generated. Use the
Watchdog timer for recovery in case this can lead to hang-up of the system.
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Effect of a Clock stop detection reset
A Clock stop detection reset asserts the global reset signal, sets the corresponding Clock stop detection reset
cause bit and puts the MCU into reset state.
The source clock timer and clock ready monitor bit of the failed clock is also cleared by the Clock stop
detection reset.
After reset release the MCU restarts in RC clock mode and the reset cause bits can be read. It is
recommended to disable the clock that caused the reset by setting the MCE or SCE bit to "0".
The contents of internal RAM memory and all registers which are not reset (initial value 'X') cannot be
guaranteed after a Clock stop detection reset.
■ Clock stop detection reset and Standby modes
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Sleep and Timer mode
The clock stop detection reset function is active in Sleep and Timer mode. This means a Main Clock stop
reset can be asserted in Run, Sleep and Timer mode if System clock CLKS1 or CLKS2 is set to Main or PLL
clock mode (as indicated by the CKMR register). A Sub Clock stop reset can be asserted in Run, Sleep and
Timer mode if System clock CLKS1 or CLKS2 is set to Sub clock mode.
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MB96300 Super Series Hardware Manual
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