Fujitsu MB96300 series Hardware Manual page 557

Table 21.2-1 Function of each bit of the bus status register (IBSRn) (2/3)
Bit name
bit 5 AL:
Arbitration loss
bit
bit 4 LRB:
Last received bit
bit 3 TRX:
Transferring data
bit
bit 2 AAS:
Addressed as
slave bit
bit 1 GCA:
General call
address bit
This bit indicates an arbitration loss.
"0": No arbitration loss detected.
"1": Arbitration loss occurred during master sending.
This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR
register.
An arbitration loss occurs if:
- the data sent does not match the data read on the SDA line at the rising SCL edge
- a repeated start condition is generated by another master in the first bit of a data byte
- The interface could not generate a start or stop condition because signal transition caused
from "1" to "0" by a certain external condition observed at the SCL line.
This bit is used to indicate the acknowledge from the receiving device.
"0": Receiver acknowledged.
"1": Receiver did not acknowledge.
It is changed by the hardware upon reception of bit 9 (acknowledge bit) and is also cleared
by a start or stop condition.
This bit indicates data transmission operation.
"0": Not transmitting data.
"1": Transmitting data.
It is set to "1":
- if a start condition was generated in master mode
- if addressed as slave in read access.
It is set to "0" if:
- the bus is idle (BB="0")
- an arbitration loss occurred
- "1" is written to the SCC bit during master interrupt (MSS="1" and INT="1")
- the MSS bit being cleared during master interrupt (MSS="1" and INT="1")
- the interface is in slave mode and the last transferred byte was not acknowledged
- the interface is in slave mode and it is receiving data
- the interface is in master mode and is reading data from a slave
This bit indicates detection of a slave addressing.
"0": Not addressed as slave.
"1": Addressed as slave.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its
seven and/or ten bit slave address.
This bit indicates detection of a general call address (0x00).
"0": General call address not received as slave.
"1": General call address received as slave.
This bit is cleared by a (repeated-) start or stop condition.
CHAPTER 21 400 kHz I
Function
2
C INTERFACE
549