Operation Of The Clock Stop Detection Function And Reset - Fujitsu MB96300 series Hardware Manual

CHAPTER 8 RESETS AND STARTUP
8.6

Operation of the Clock stop detection function and reset

This section describes the operation of the clock stop detection circuit that detects a
failure of the external Main or Sub oscillator.
■ Function of the clock stop detection circuit
The clock stop detection circuit observes the oscillation of the Main and Sub clock. If no rising edge of the
observed clock was detected within a selected interval although the clock was enabled, then the
corresponding clock missing flag is set. This function is always active when the RC oscillator is enabled.
An additional Clock stop reset can be asserted if the failed clock was currently used for the System clocks
CLKS1 or CLKS2 or the Watchdog timer to avoid a hang-up of the MCU. After such a reset the MCU
always changes to RC clock mode where the CPU can check the reset cause and put the MCU into a safe
state.
■ Configuration of the clock stop detection circuit
The clock stop detection circuit has 3 configuration bits, one for activating the clock stop reset function and
two for selecting the detection interval.
●
Clock Stop Detection Reset Enable bit (RCR: CSDRE)
The initial value of the CSDRE bit after any reset is "0" (Clock stop detection reset disabled). Setting this bit
to "1" activates the clock stop detection reset function and writing "0" disables the function. However writing
to the CSDRE bit is possible only when the System clock 1 (CLKS1) is set to RC clock.
●
Clock Stop Detection Interval select bits (RCR: MCSDI and SCSDI)
A missing clock is detected when no rising edge of the observed clock was detected within a certain interval
time. This interval is a certain number of RC clock cycles and therefore depends on the selected RC clock
frequency. Two bits allow a selection of this interval to adjust the observation time to the selected RC clock
frequency and the observed external clock frequency.
Table 8.6-1 Clock stop detection interval
Observed
clock
Main clock
220
Select
Setting
bit
0 (initial value)
MCSDI
1
MB96300 Super Series Hardware Manual
Clock Stop Detection Interval
RC clock Time for RC clock
cycles frequency of
2MHz (min - max) /
(minimum
external
frequency)
6 - 8 1.5µs - 8µs /
(~700kHz)
3 - 4 0.75µs - 4µs /
(~1.4MHz)
Time for RC clock
frequency of
100kHz (min - max)
/ (minimum
external
frequency)
30µs - 160µs /
(~35kHz)
15µs - 80µs /
(~70kHz)