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MB96300 Super Series Hardware Manual
Figure 20.8-1 Baud Rate Detection Using the Input Capture Units
Pin IN4
LIN-UART4
Pin IN5
LIN-UART5
If the PFR bit equals '1' and the EPFR bits equals '0', the ICU is connected to its corresponding input pin IN.
If the PFR bit equals '1' and the EPFR bits equals '1', the USARTs are connected to the ICU.
The user has to take into account that:
ICU4 and ICU5 share one free running timer (prescaler).
Effects of reception errors and CRE bit.
CRE resets reception state machine and next falling edge at SINn starts reception of new byte. Therefore
either set CRE bit immediately (within half bit time) after receiving errors to prevent data stream
desynchronization or wait an application dependent time after receiving errors and set CRE, when SINn is
idle.
CRE bit timing within 1/2 Bit Time of Stop Bit
Last Data Bit
SIN
Sample
Point
Error
Flags
CRE
Reception State Machine is reset
Falling edge detected: Receive new Frame
PFR[4] & EPFR[4]
LSYN
PFR[5] & EPFR[5]
LSYN
Figure 20.8-2 Timing of the CRE bit
Stop Bit
Start Bit
1/2 Bit Time
10
11
IN
S
Free-Run TIMER4
10
11
IN
S
CRE bit timing out of 1/2 Bit Time of Stop Bit
Last Data Bit
Stop Bit
1/2 Bit Time
SIN
Sample
Point
Error
Flags
CRE
Falling edge detected: Receive new Frame
Reception State Machine is reset, Start Bit Condition
is reset, actal Reception is desznchronized
CHAPTER 20 USART
ICU4
ICU5
Start Bit
537
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