Operation Of A/D Converter - Fujitsu MB96300 series Hardware Manual

CHAPTER 18 A/D CONVERTER
18.3

Operation of A/D Converter

The A/D converter operates using the sequential-comparison converter system; and 10
bits or 8 bits can be selected for the A/D converter's resolution.
Since this A/D converter has only one register (10 bits; conversion result data register
ADCR) for storing conversion results, this register is rewritten every time conversion is
ended. So, this A/D converter alone is not suitable for continuous conversion; and
therefore conversion be performed with transferring converted data to the memory using
the DMA is recommended.
■ Single mode 1 / 2
In the single mode, analog inputs from the starting channel set by the ANS bits to the ending channel set by
the ANE bits are sequentially converted; and when conversion of the ending channel is ended, A/D
conversion is stopped. When the starting channel and the ending channel are the same (ANS = ANE),
conversion is performed for only the channel set by the ANS bits.
Example:
ANS = 00000
Start --> AN0 --> AN1 --> AN2 --> AN3 --> End
ANS = 00010
Start --> AN2 --> End
■ Continuous mode
In the continuous mode, A/D conversion is repeated until "0" is written to the BUSY bit (when "0" is written
to the BUSY bit, operation of the A/D converter is forced to stop).
Note that when operation of the A/D converter is forced to stop, A/D conversion may stop halfway. In this
case, the conversion result register contains the previous data for which conversion completed.
■ Stop mode
In the stop mode, analog inputs from the starting channel set by the ANS bits to the ending channel set by the
ANE bits are sequentially converted, but every time one channel is converted, conversion stops.
When conversion of the ending channel is ended, control returns to the starting channel to continue A/D
conversion. When the starting channel and the ending channel are the same (ANS = ANE), conversion is
performed for only one channel.
Example:
ANS = 00000
Start --> AN0 --> Stop --> Start --> AN1 --> Stop --> Start --> AN2 --> Stop --> Start --> AN3 --> Stop
--> Start --> AN0 -->-->--> Repetition of sequence
ANS = 00010
Start --> AN2 --> Stop --> Start --> AN2 --> Stop --> Start --> AN2 -->-->--> Repetition of sequence
In the above sequences, only A/D activation causes set using the STS1 and STS0 bits are valid.
The start of conversion can be synchronized by this mode.
452
, ANE = 00011 :
B B
, ANE = 00010 :
B B
, ANE = 00011 :
B B
, ANE = 00010 :
B B
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