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MB96300 Super Series Hardware Manual
bit detection circuit detects start bits from the serial input signal and sends a signal to the reload counter to
synchronize it to the falling edge of these start bits. The reception parity counter calculates the parity of the
reception data.
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Reception Shift Register
The reception shift register fetches reception data input from the SINn pin, shifting the data bit by bit. When
reception is complete, the reception shift register transfers receive data to the RDRn register.
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Reception Data Register (RDRn)
This register retains reception data. Serial input data is converted and stored in this register.
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Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. When the
transmission of one data item of the specified data length is complete, the transmission bit counter sets the
Transmission data register full flag. The transmission start circuit starts transmission when data is written to
TDRn. The transmission parity counter generates a parity bit for data to be transmitted if parity is enabled.
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Transmission Shift Register
The transmission shift register transfers data written to the TDRn register to itself and outputs the data to the
SOTn pin, shifting the data bit by bit.
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Transmission Data Register (TDRn)
This register sets transmission data. Data written to this register is converted to serial data and output.
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Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
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Oversampling Unit
The oversampling unit oversamples the incoming data at the SINn pin for five times. It is switched off in
synchronous operation mode.
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Interrupt Generation Circuit
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a
corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
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LIN synch Break and Synchronization Field Detection Circuit
The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is
sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth
falling edge of the synchronization field is recognized by this circuit by generating an internal signal for the
Input Capture Unit to measure the actual serial clock time of the transmitting master node.
CHAPTER 20 USART
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