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MB96300 Super Series Hardware Manual
3.3
Interrupt Control Registers (ICR)
For each peripheral resource that has an interrupt function, there is an interrupt control
register (ICR). The interrupt control register sets the interrupt level (IL) for the peripheral
resource it is assigned to.
■ Interrupt control register (ICR)
Figure 3.3-1 "Interrupt control register (ICR)" is a diagram of the bit configuration of the interrupt control
register.
Address:
0x3A1
Read/Write:
Initial Value:
Address:
0x3A0
Read/Write:
Initial Value:
−:
no access
readable and writable
R/W:
ICR [bits 15 to 8]: IX[7:0] Index of the interrupt level (IL) to be accessed
These bits are readable and writable, and specify the index of the interrupt level of the corresponding
internal resource. It selects the number of the interrupt level to be accessed. IL[n] belongs to the
peripheral interrupt request number IRQ[n], which both are related to the interrupt INT[n].
The system interrupts INT0 to INT11 have a fixed priority and thus have no interrupt levels. Writing to
interrupt levels below the index of 12 has no effect, reading returns an undefined value. The same
restriction applies for not available hardware interrupts above a device dependent maximum interrupt
number.
At reset IX is initialized to 0, thus no valid interrupt level register is selected.
Figure 3.3-2 "Relationship between index (IX), level (IL) and IRQ number, example for IX = 20"
illustrates the access to level registers by the IX pointer. The dashed line around IX and the selected IL
shows the actual contents of the ICR.
Level configuration is written to or read from IL, where IX points to. To write the level configuration to a
dedicated IL, specify the according index by writing IX before or simultaneously by word access. To read
from a dedicated IL, IX must be written before reading IL.
Caution for the use of concurrent tasks:
In the case of concurrent tasks accessing the interrupt level information, be careful at the handling of the
Figure 3.3-1 Interrupt control register (ICR)
15
14
13
12
IX7
IX6
IX5
IX4
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
0
0
0
0
7
6
5
4
−
−
−
−
(−)
(−)
(−)
(−)
X
X
X
X
11
10
9
8
IX3
IX2
IX1
IX0
1
1
0
0
3
2
1
0
−
IL2
IL1
IL0
(−)
(R/W) (R/W) (R/W)
X
1
1
1
CHAPTER 3 INTERRUPTS
Bit No.
ICR: IX
Bit No.
ICR: IL
95
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