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CHAPTER 7 CLOCK MODULATOR
F0:
T0:
resolution:
F
:
min
F
:
max
phase skew:
phase skew 50:
CMPR:
reference clock
modulated clock
The table below shows the recommended setting for several MCU clocks and modulation parameters:
Table 7.2-4 Modulation Parameter recommended settings (1/2)
F0 (MHz)
resolution
16
3
16
11
16
3
186
Frequency of unmodulated input clock (PLL frequency)
Period of unmodulated input clock (PLL clock period)
resolution of frequencies in the modulated clock. low (1) to high (7)
minimal frequency occurring in the modulated clock
maximal frequency occurring in the modulated clock
The maximal phase shift of the modulated clock relative to the unmodulated
reference clock in terms of clock periods of the unmodulated clock.
Example: phase skew=1.44
In worst case, a sequence of n periods of the modulated clock can be 1.44*T0
shorter or 1.44*T0 longer than a sequence of n periods of the unmodulated
reference clock.
n can be any number > 50 periods
phase skew for sequences with n<= 50 periods
register setting of the CMPR register
n periods
n periods
n periods
mod
F
(MHz)
min
degree
1
13.47
1
12.19
2
14.22
MB96300 Super Series Hardware Manual
F
+/- phase
max
skew
(MHz)
50
[periods]
19.69
1.5625
23.72
2.25
18.29
1.0625
± phase skew
+/- phase
CMPR
skew
min/max
[periods]
3.7187
026F
7.875
036B
2.875
046E
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