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MB96300 Super Series Hardware Manual
Figure 10.2-2 Configuration of the RC Clock Timer Control Register (RCTCR)
7
Address:
000408
-
RCTIE RCTIF RCTR RCTI3
H
-
R/W R/W
X
: undefined value
W
: Write only (read always returns "1")
R/W
: Readable and writable
: Initial value
6
5
4
3
2
1
0
RCTI2 RCTI1 RCTI0
W
R/W
R/W R/W R/W
bit3
RCTI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CHAPTER 10 SOURCE CLOCK TIMERS
Initial value
X 0 0 1 0 0 0 0
B
bit2
bit1
bit0
RC Clock Timer Interrupt interval
(The corresponding time for the
RCTI2
RCTI1
RCTI0
nominal RC clock frequency of 2MHz
and 100kHz is given in parentheses)
8
0
0
0
2
/ CLKRC (approx. 128µs/2.5ms)
9
0
0
1
2
/ CLKRC (approx. 256µs/5.1ms)
10
0
1
0
2
/ CLKRC (approx. 512µs/10.2ms)
11
0
1
1
2
/ CLKRC (approx. 1ms/20.5ms)
12
1
0
0
2
/ CLKRC (approx. 2ms/41ms)
13
1
0
1
2
/ CLKRC (approx. 4ms/82ms)
14
1
1
0
2
/ CLKRC (approx. 8ms/164ms)
15
1
1
1
2
/ CLKRC (approx. 16ms/328ms)
16
0
0
0
2
/ CLKRC (approx. 32ms/655ms)
17
0
0
1
2
/ CLKRC (approx. 65ms/1.3s)
18
0
1
0
2
/ CLKRC (approx. 131m/2.6s)
19
0
1
1
2
/ CLKRC (approx. 262ms/5.2s)
20
1
0
0
2
/ CLKRC (approx. 524ms/10.4s)
21
1
0
1
2
/ CLKRC (approx. 1.05s/21s)
22
1
1
0
2
/ CLKRC (approx. 2.1s/42s)
23
1
1
1
2
/ CLKRC (approx. 4.2s/84s)
bit4
RC Clock Timer Reset bit
RCTR
Read
0
always reads 1
1
bit5
RC Clock Timer Interrupt Flag
RCTIF
Read
0
no interrupt
1
interrupt requested
bit6
RCTIE
RC Clock Timer Interrupt Enable bit
0
Disable Interrupt
1
Enable Interrupt
bit7
-
Reserved
0
Always write "0" to this bit
Write
reset all bits to 0
no effect
Write
clear this bit
no effect
265
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