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MB96300 Super Series Hardware Manual
5.2
Delayed Interrupt Register
DIRR controls request and cancellation of the Delayed Interrupt. Writing "1" to this
register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt
request.
■ Delayed Interrupt Cause Issuance/Cancellation register (DIRR: Delayed Interrupt
Request Register)
Figure 5.2-1 Delayed Interrupt Cause/Cancel Register (DIRR)
Address:
0x3A4
Read/Write:
Initial Value:
Readable and writable
R/W:
Undefined bit; read returns undefined value, write always 0 to this bit
−:
Table 5.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR)
Bit name
bit 7 to bit 1
-:
Undefined bit
bit 0
R0:
Delayed interrupt
request output bit
7
6
5
4
−
−
−
−
(−)
(−)
(−)
(−)
X
X
X
X
• When these bits are read, the values are undefined.
• Writing to these bits does not affect operation.
• Write always '0' to this bit
• This bit sets the generation/cancel of a delayed interrupt request.
• When this bit is "1", a delayed interrupt request is output.
• When this bit is "0", the delayed interrupt request is cleared.
• This bit is cleared after reset.
CHAPTER 5 DELAYED INTERRUPT
3
2
1
0
−
−
−
R0
(−)
(−)
(−)
(R/W)
X
X
X
0
Function
Bit No.
DIRR
141
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