Table of Contents
Advertisement
MB96300 Super Series Hardware Manual
capture module represents 8 times of the baud rate clock cycle.
Therefore, baud rate setting value is summarized as follows:
without timer overflow : BGRn value = (b-a)/8
with timer overflow
where max is the timer maximum value at the overflow occurs.
where a is the value of the ICU counter register after the first Interrupt
where b is the value of the ICU counter register after the second Interrupt
For the correspondence between other USARTs and ICUs, see 14.3 "16-bit Free-Running Timer".
●
LIN Synch Break Detection Interrupt and Flags
If a LIN Synch synchronization break is detected in the slave mode, the LIN Break Detected (LBD) flag of
the ESCRn is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is set.
Figure 20.7-6 LIN synch break detection and flag set timing.
Serial clock
cycle#
Serial
clock
Serial
Input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs, if RXE=1
The figure above demonstrates the LIN synch break detection and flag set timing.
Note, that if reception is enabled (RXE = 1) and receive interrupt is enabled (RIE = 1) the Reception Data
Framing Error (FRE) flag bit of the SSRn will cause a receive interrupt 2 bit times ("8N1") earlier than the
LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected.
LBD is only supported in operation mode 3.
The Figure 20.7-7 "USART behavior as slave in LIN mode" shows a typical start of a LIN message frame
and the behavior of the USART.
: BGRn value = (max + b-a)/8
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reception interrupt occurs, if RXE=0
CHAPTER 20 USART
521
Advertisement
Table of Contents
