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CHAPTER 6 CLOCKS
used for the System clock 2, the watchdog or clock stop detect function. Disabling these clocks also
disables the corresponding source clock timers.
■ Clock source switching
Clock source switching means changing the clock source for CLKS1 or CLKS2.
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Changing the clock source
• The clock source selection can be done independently for CLKS1 and CLKS2
• A clock source switching is done by writing a new value to the System clock select bits (SC1S[1:0] for
System clock 1 and SC2S[1:0] for System clock 2)
• A transition to a different clock source is possible only when the selected clock is ready (means the
corresponding ready flag RCM, MCM, PCM or SCM in the Clock Monitor Register CKMR is set).
• If the selected clock is ready, then the clock source transition will be executed by starting the
synchronization mechanism. The System Clock Monitor bits (SC1M for System clock 1 and SC2M for
System clock 2) of the Clock Monitor register change to the new value after completion of this clock
switching.
• Writing a second value to the System clock select bits before switching to the mode selected before has
completed, cancels the first transition request.
• If the selected clock is not available or not stabilized, then switching to the new clock mode will be
delayed until the selected clock is available and stable (clock ready flag CKMR: RCM, MCM, PCM or
SCM set).
• After Stop mode release by interrupt, the System Clock Selectors directly select the clocks which are
defined by the SC1S/SC2S bits, irrespective of the clock ready monitor bits. Hence do not select an
unavailable clock before switching to Stop mode because this clock is used for the restart by an
interrupt.
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Reset and clock source
The clock source for both System clocks (CLKS1 and CLKS2) is set to RC clock (CLKRC) by any reset.
The RC clock stabilization time of 64 RC clock cycles is applied after each reset.
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Access to peripheral resources clocked with CLKP2 or CLKP3
Do not access (read or write) any resource clocked with the peripheral clock 2 (CLKP2) directly after
changing the setting of the SC1S or SC2S bits. Do always make sure that the requested clock transition has
completed by reading the SC1M/SC2M monitor bits. Access to resources clocked with CLKP2 is allowed
only if SC1M[1:0] equals to SC1S[1:0] and SC2M[1:0] equals to SC2S[1:0].
■ Activating and Disabling source clocks
• After each reset, the Main oscillator, Sub oscillator and RC oscillator are enabled while the PLL
multiplier circuit is disabled.
• Source clocks selected for the System clocks CLKS1 or CLKS2 are always activated.
• Source clocks not used for the System clocks can be enabled and disabled with the corresponding enable
bits in the CKSR register.
• Disable a source clock for current saving by setting the corresponding enable bit in the CKSR register to
"0".
• Enable a source clock if it is needed for a certain function or for a fast System clock changing by setting
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