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CHAPTER 8 RESETS AND STARTUP
Figure 8.5-2 Configuration of the Reset Configuration Register (RCR)
7
Address:
00040C
-
H
-
X
: undefined value
R/W
: Readable and writable
W
: Write only
: Initial value
Table 8.5-1 Function Description of Each Bit of the Reset Configuration Register (RCR) (1/3)
Bit name
bit 0
SRSTG:
Software Reset
Generation bit
210
6
5
4
3
2
1
0
LVDE LVRE SRSTG
-
SCSDI MCSDI CSDRE
-
R/W R/W R/W
R/W R/W
W
• When "1" is written to this bit, an internal Software reset is generated.
• Writing "0" to this bit has no effect.
• The read value of this bit is always "0".
MB96300 Super Series Hardware Manual
Initial value
X X 0 0 0 1 1 0
B
bit0
SRSTG
Software Reset Generation bit
0
No effect on operation
1
Software reset is generated
bit1
LVRE
Low Voltage Reset Enable bit
0
Low Voltage reset function disabled
1
Low Voltage reset function activated
bit2
LVDE
Low Voltage Detector Enable bit
0
Low Voltage Detector disabled
1
Low Voltage Detector activated
bit3
CSDRE
Clock Stop Detection Reset Enable bit
0
Clock stop detection reset function disabled
1
Clock stop detection reset function activated
bit4
MCSDI
Main Clock Stop Detection Interval select bit
0
Main clock stop detection interval is 6-8 RC clock cycles
1
Main clock stop detection interval is 3-4 RC clock cycles
bit5
SCSDI
Sub Clock Stop Detection Interval select bit
0
Sub clock stop detection interval is 384-512 RC clock cycles
1
Sub clock stop detection interval is 24-32 RC clock cycles
bit6 - bit7
-
Reserved
0
Always write "0" to these bits
Function
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