Tamper Detection - ST STM32G0 1 Series Reference Manual

RM0444
31.3.4

Tamper detection

The tamper detection can be configured for the following purposes:
•
erase the backup registers (default configuration)
•
generate an interrupt, capable to wakeup from Stop and Standby mode
•
generate a hardware trigger for the low-power timers
TAMP backup registers
The backup registers (TAMP_BKPxR) are not reset by system reset or when the device
wakes up from Standby mode.
The backup registers are reset when a tamper detection event occurs except if the
TAMPxNOER bit is set, or if the TAMPxMSK is set in the TAMP_CR2 register.
Note: The backup registers are also erased when the readout protection of the flash is changed
from level 1 to level 0.
Tamper detection initialization
Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the TAMP_CR
register.
Each TAMP_INx tamper detection input is associated with a flag TAMPxF in the TAMP_SR
register.
When TAMPxMSK is cleared:
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided
below:
•
3 ck_apre cycles when TAMPFLT differs from 0x0 (level detection with filtering)
•
3 ck_apre cycles when TAMPTS = 1 (timestamp on tamper event)
•
No latency when TAMPFLT = 0x0 (edge detection) and TAMPTS = 0
A new tamper occurring on the same pin during this period and as long as TAMPxF is set
cannot be detected.
When TAMPxMSK is set:
A new tamper occurring on the same pin cannot be detected during the latency described
above and 2.5 ck_rtc additional cycles.
By setting the TAMPxIE bit in the TAMP_IER register, an interrupt is generated when a
tamper detection event occurs (when TAMPxF is set). Setting TAMPxIE is not allowed when
the corresponding TAMPxMSK is set.
Trigger output generation on tamper event
The tamper event detection can be used as trigger input by the low-power timers.
When TAMPxMSK bit in cleared in TAMP_CR register, the TAMPxF flag must be cleared by
software in order to allow a new tamper detection on the same pin.
When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR
register. This configuration allows to trig automatically the low-power timers in Stop mode,
without requiring the system wakeup to perform the TAMPxF clearing. In this case, the
backup registers are not cleared.
Tamper and backup registers (TAMP)
RM0444 Rev 5 915/1390
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