Usart Interrupt Flag Clear Register (Usart_Icr) - ST STM32G0 1 Series Reference Manual

Universal synchonous receiver transmitter (USART)
Bit 2 NE: Noise detection flag
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
Bit 1 FE: Framing error
Bit 0 PE: Parity error
33.8.11

USART interrupt flag clear register (USART_ICR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. UDRCF EOBCF RTOCF
w
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 WUCF: Wakeup from low-power mode clear flag
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
1080/1390
This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NECF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
which itself generates an interrupt. An interrupt is generated when the NE flag is set
during multi buffer communication if the EIE bit is set.
When the line is noise-free, the NE flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to
Tolerance of the USART receiver to clock deviation on page
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
When transmitting data in Smartcard mode, this bit is set when the maximum number of
transmit attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the USART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. CTSCF LBDCF
w w w
Writing 1 to this bit clears the WUF flag in the USART_ISR register.
must be kept at reset value.
page 1000.
Writing 1 to this bit clears the CMF flag in the USART_ISR register.
24 23 22
Res. Res. Res. Res.
8 7 6
TCBGT TXFEC
TCCF
CF
w w w
Refer to Section 33.4: USART implementation on
RM0444 Rev 5
Section 33.5.8:
1018).
21 20 19 18
WUCF Res. Res.
w
5 4 3 2
IDLECF ORECF NECF
F
w
w w w
RM0444
17 16
CMCF Res.
w
1 0
FECF PECF
w w