Lptim Interrupt Clear Register (Lptim_Icr); Lptim Interrupt Enable Register (Lptim_Ier) - ST STM32G0 1 Series Reference Manual

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LPTIM interrupt clear register (LPTIM_ICR)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWNCF: Direction change to down clear flag

Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 26.3: LPTIM

Bit 5 UPCF: Direction change to UP clear flag

Writing 1 to this bit clear the UP flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 26.3: LPTIM

Bit 4 ARROKCF: Autoreload register update OK clear flag

Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register

Bit 3 CMPOKCF: Compare register update OK clear flag

Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register

Bit 2 EXTTRIGCF: External trigger valid edge clear flag

Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register

Bit 1 ARRMCF: Autoreload match clear flag

Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register

Bit 0 CMPMCF: Compare match clear flag

Writing 1 to this bit clears the CMPM flag in the LPTIM_ISR register

Address offset: 0x008

Reset value: 0x0000 0000

implementation.

RM0444 Rev 5

Low-power timer (LPTIM)

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