Figure 126. Control Circuit In External Clock Mode 1; Figure 127. External Trigger Input Block - ST STM32G0 1 Series Reference Manual

Advanced-control timer (TIM1)
Counter clock = CK_CNT = CK_PSC
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 127
TIMx_AF1[17:14]
ETR pin
(1)
1. Refer to Figure 123: TIM1 ETR input
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
544/1390

Figure 126. Control circuit in external clock mode 1

TI2
CNT_EN
Counter register
TIF
gives an overview of the external trigger input block.

Figure 127. External trigger input block

ETR
0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
circuitry.
34
Write TIF=0
or
ETRP
Filter
f downcounter
DTS
ETF[3:0]
(internal clock)
TIMx_SMCR
RM0444 Rev 5
35
TI2F or
TI1F or
Encoder
mode
TRGI
External clock
mode 1
ETRF External clock
mode 2
Internal clock
CK_INT
mode
ECE SMS[2:0]
TIMx_SMCR
RM0444
36
MS31087V2
CK_PSC
MSv40118V1