Interconnect matrix
9
Interconnect matrix
9.1
Introduction
Several peripherals have direct connections between them.
This allows autonomous communication and/or synchronization between peripherals,
saving CPU resources thus power consumption.
In addition, these hardware connections remove software latency and allow design of
predictable systems.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep, Stop 0, and Stop 1 modes.
For availability of peripherals on different STM32G0x1 products, refer to
Availability of
9.2
Connection summary
Source
TIM1
-
9.3.1
TIM2
9.3.1
-
TIM3
9.3.1
9.3.1
TIM4
9.3.1
9.3.1
TIM14
-
9.3.1
TIM15
9.3.1
9.3.1
TIM16
-
-
TIM17
9.3.1
-
TIM6
-
-
TIM7
-
-
LPTIM1
-
-
LPTIM2
-
-
USART1
-
-
USART4
-
-
ADC
9.3.3
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T. sensor
-
-
VBAT
-
-
270/1390
peripherals.
Table 45. Interconnect matrix
9.3.1
9.3.1
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9.3.1
9.3.1
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9.3.1
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-
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9.3.1
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-
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9.3.1
9.3.1
9.3.1
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-
9.3.1
9.3.1
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-
-
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9.3.1
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-
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9.3.1
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
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-
-
(1)(2)
Destination
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-
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-
-
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-
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-
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RM0444 Rev 5
Section 1.4:
9.3.2
9.3.4
-
9.3.7
9.3.2
9.3.4
-
9.3.7
9.3.2
9.3.4
-
9.3.7
9.3.2
9.3.4
-
9.3.7
-
-
9.3.12
-
9.3.2
9.3.4
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-
-
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-
-
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9.3.2
9.3.4
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9.3.4
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9.3.4
9.3.12
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9.3.4
9.3.12
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9.3.8
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9.3.8
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RM0444
9.3.7
9.3.7
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9.3.7
9.3.7
-
9.3.7
9.3.7
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9.3.7
9.3.7
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9.3.11
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9.3.11
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9.3.11
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9.3.11
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