Rcc Registers; Clock Control Register (Rcc_Cr) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
5.4

RCC registers

Unless otherwise specified, the RCC registers support word, half-word, and byte access,
without any wait state.
5.4.1

Clock control register (RCC_CR)

Address offset: 0x00
Power-on reset value: 0x0000 0500
Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous
value.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. HSIDIV[2:0]
rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to
of peripherals.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable the PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bit 23 HSI48RDY: HSI48 clock ready flag
The flag is set when the HSI48 clock is ready for use.
Bit 22 HSI48ON: HSI48 RC oscillator enable
0: Disable
1: Enable
Bits 21:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector
is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE
clock failure is detected. This bit is set only and is cleared by reset.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).
178/1390
28 27 26 25
PLL
Res. Res.
RDY
r
12 11 10 9
HSI HSI
RDY KERON
rw rw r rw
24 23 22
HSI48 HSI48
PLLON Res.
(1) (1)
RDY ON
rw r rw
8 7 6
HSION Res. Res. Res.
rw
(1)
(1)
RM0444 Rev 5
21 20 19 18
CSS HSE
Res.
ON BYP
rs rw
5 4 3 2
Res. Res. Res.
Section 1.4: Availability
RM0444
17 16
HSE HSE
RDY ON
r rw
1 0
Res. Res.