Figure 207. Gating Tim2 With Enable Of Tim3; Figure 208. Triggering Tim2 With Update Of Tim3 - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4)
TIM3-CEN=CNT_EN
TIM3-CNT_INIT
TIM2-CNT_INIT
TIM2-write CNT
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 3. Refer to
Figure 204
non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write '0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (f
1. Configure TIM3 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM3_CR2 register).
2. Configure the TIM3 period (TIM3_ARR registers).
3. Configure TIM2 to get the input trigger from TIM3 (TS=00010 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM3 by writing '1 in the CEN bit (TIM3_CR1 register).
TIM2-CEN=CNT_EN
666/1390

Figure 207. Gating TIM2 with Enable of TIM3

CK_INT
TIM3-CNT
75
TIM2-CNT
AB
TIM2-TIF
for connections. Timer 2 starts counting from its current value (which can be

Figure 208. Triggering TIM2 with update of TIM3

CK_INT
TIM3-UEV
TIM3-CNT
FD
TIM2-CNT
TIM2-TIF
RM0444 Rev 5
00
00 E7
Write TIF = 0
FE FF 00
45
Write TIF = 0
01 02
E8 E9
= f
CK_CNT CK_INT
01 02
46 47 48
RM0444
MS33120V1
/3).
MS33121V1