Direct Memory Access Controller (Dma); Introduction; Dma Main Features - ST STM32G0 1 Series Reference Manual

RM0444
10

Direct memory access controller (DMA)

10.1

Introduction

The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
Refer to
Each channel is dedicated to managing memory access requests from one or more
peripherals. The DMA includes an arbiter for handling the priority between DMA requests.
10.2

DMA main features

•
Single AHB master
•
Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
•
Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
•
All DMA channels independently configurable:
–
–
–
–
–
•
Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
Section 10.3 for information on DMA implementation.
Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
Support of transfers from/to peripherals to/from memory with circular buffer
management
Programmable number of data to be transferred: 0 to 2
Direct memory access controller (DMA)
RM0444 Rev 5
16
- 1
277/1390
297