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RM0444
16.7.15
DAC calibration control register (DAC_CCR)
Address offset: 0x38
Reset value: 0x00XX 00XX
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:16 OTRIM2[4:0]: DAC channel2 offset trimming value
These bits are available only on dual-channel DACs. Refer to
implementation.
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC channel1 offset trimming value
16.7.16
DAC mode control register (DAC_MCR)
Address offset: 0x3C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bits 23:19 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0444 Rev 5
Digital-to-analog converter (DAC)
21
20
19
18
Res.
OTRIM2[4:0]
rw
rw
rw
5
4
3
2
Res.
OTRIM1[4:0]
rw
rw
rw
Section 16.3: DAC
21
20
19
18
Res.
Res.
Res.
rw
5
4
3
2
Res.
Res.
Res.
rw
17
16
rw
rw
1
0
rw
rw
17
16
MODE2[2:0]
rw
rw
1
0
MODE1[2:0]
rw
rw
435/1390
441
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