Figure 10. Clock Tree - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
LSI RC
32 kHz
LSCO
OSC32_OUT
LSE OSC
32.768 kHz
OSC32_IN
Clock
detector
MCO
/ 1...1024
(2)
MCO2
/ 1...1024
OSC_OUT
HSE OSC
4-48 MHz
OSC_IN
Clock
detector
HSI48 RC
CRS
48 MHz
HSI16 RC
16 MHz
PLL
VCO
x /M
f
/N
VCO
f
/ R PLLR
f
PLLQ
/ Q
f
PLLP
/ P
I2S_CKIN
BOLD: clock origin
1. Only applies to STM32G071xx and STM32G081xx and to STM32G0B1xx and STM32G0C1xx.
2. Only applies to STM32G0B1xx and STM32G0C1xx.
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Figure 10. Clock tree

LSI
LSI
LSE
LSE
LSE
LSI
SYSCLK
HSE
HSI16
(2)
HSI48
PLLRCLK
(2)
PLLQCLK
(2)
PLLPCLK
(2)
RTCCLK
(2)
RTC WAKEUP
HSE
PLLRCLK
HSISYS
HSI48
/1...128
HSI16
HSE
f
PLLIN
HSI16
PLLRCLK
PLLQCLK
PLLPCLK
LSI
LSE
HSE
/32
AHB
HCLK
PRESC
/ 1,2,..512
LSE
LSI
SYSCLK
HSE
HSISYS
/ 8
HSI16
RM0444 Rev 5
RTC WAKEUP
RTCCLK
LSE
HSI16
/ 488
HSI16
to AHB bus, core, memory and DMA
FCLK Cortex free-running clock
HCLK8 to Cortex system timer
/ 8
APB
to APB peripherals
PCLK
PRESC
/ 1,2,4,8,16
PCLK
LSE
HSI16
SYSCLK
PCLK
HSI16
SYSCLK
PCLK
LSI
LSE
HSI16
x1, x2
to TIM2/3/4/6/7/14/16/17
TIMPCLK
TIMPCLK
PLLQCLK
HSI48
PLLQCLK
/1,2,4,8
SYSCLK
SYSCLK
async clock to ADC
HSI16
PLLPCLK
SYSCLK
PLLPCLK
HSI16
I2S_CKIN
HSI48
HSE
PLLQCLK
PCLK
HSE
PLLQCLK
RM0444
to IWDG
from RTC
to RTC
to CEC
(1)
to UCPD1/2
to PWR
to USART1
LPUART1
LPUART2
(1)
USART2
USART3
to I2C1
I2C2
to LPTIM1/2
LPTIMx_IN
to TIM1
(1)
TIM15
to RNG
to I2S1
I2S2
(2)
to USB
(2)
to FDCAN