Figure 161. General-Purpose Timer Block Diagram - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4)
TIMx_ETR
On-chip ETR
sources
XOR
TI1[0]
TIMx_CH1
TI1[1..15]
TI2[0]
TIMx_CH2
TI2[1..15]
TI3[0]
TIMx_CH3
TI3[1..15]
TI4[0]
TIMx_CH4
TI4[1..15]
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
626/1390

Figure 161. General-purpose timer block diagram

Internal clock (CK_INT)
From RCC
ETR
Polarity selection & edge
detector & prescaler
ITR[0..15]
TI1F_ED
CK_PSC
Input
TI1
TI1FP1
filter &
IC1
TI1FP2
edge
detector
TRC
Input
TI2FP1
IC2
filter &
TI2
TI2FP2
edge
TRC
detector
Input
TI3FP3
filter &
IC3
TI3
TI3FP4
edge
detector
TRC
Input
TI4FP3
filter & IC4
TI4
TI4FP4
edge
TRC
detector
ETRF
ETRP
Input filter
TRG
ITR
TRC TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
prescaler
CC1I
U
IC1PS
Capture/Compare 1 register
Prescaler
CC2I
U
IC2PS
Capture/Compare 2 register
Prescaler
CC3I
U
IC3PS
Capture/Compare 3 register
Prescaler
CC4I
U
IC4PS
Capture/Compare 4 register
Prescaler
ETRF
RM0444 Rev 5
Trigger
controller
TRGO
to other timers
to peripherals
Slave
Reset, enable, count
controller
mode
Encoder
interface
UI
U
CC1I
OC1REF
Output
control
CC2I
Output
OC2REF
control
CC3I
OC3REF
Output
control
CC4I
Output
OC4REF
control
RM0444
OC1
TIMx_CH1
OC2
TIMx_CH2
OC3
TIMx_CH3
OC4
TIMx_CH4
MSv62393V2