Spix_I2S Prescaler Register (Spix_I2Spr) - ST STM32G0 1 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
35.9.9

SPIx_I2S prescaler register (SPIx_I2SPR)

Address offset: 0x20
Reset value: 0x0002
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in
master mode.
It is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: Real divider value is = I2SDIV *2
1: Real divider value is = (I2SDIV * 2) + 1
Refer to
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in
master mode.
It is not used in SPI mode.
Bits 7:0 I2SDIV[7:0]: I2S linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to
Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is
in master mode.
They are not used in SPI mode.
1194/1390
12 11 10 9
Res. Res. MCKOE
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Section 35.7.3 on page
Section 35.7.3 on page
8 7 6
ODD
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1174.
1174.
RM0444 Rev 5
5 4 3 2
I2SDIV[7:0]
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RM0444
1 0
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