Power Port C Pull-Down Control Register (Pwr_Pdcrc); Power Port D Pull-Up Control Register (Pwr_Pucrd) - ST STM32G0 1 Series Reference Manual

Power control (PWR)
31 30 29
Res. Res. Res. Res.
15 14 13
PU15 PU14 PU13 PU12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port C pull-up bit y (y = 0 to 15)
Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3
register is set activates a pull-up device on the PC[y] I/O.
1. In STM32G031xx and STM32G041xx as well as STM32G051xx and STM32G061xx devices, the
4.4.13

Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31 30 29
Res. Res. Res. Res.
15 14 13
PD15 PD14 PD13 PD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PDy: Port C pull-down bit y (y = 0 to 15)
Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down
device on the PC[y] I/O.
1. In STM32G031xx and STM32G041xx as well as STM32G051xx and STM32G061xx devices, the
4.4.14

Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
154/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
PU11 PU10 PU9
rw rw rw rw
bits PD0 to PD5 and PD8 to PD12 are reserved.
APB peripheral reset register 1
28 27 26 25
Res. Res. Res.
12 11 10 9
PD11 PD10 PD9
rw rw rw rw
bits PD0 to PD5 and PD8 to PD12 are reserved.
APB peripheral reset register 1
24 23 22
Res. Res. Res.
8 7 6
PU8 PU7 PU6
rw rw rw
(1)
(RCC_APBRSTR1).
24 23 22
Res. Res. Res.
8 7 6
PD8 PD7 PD6
rw rw rw
(1)
(RCC_APBRSTR1).
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PU5 PU4 PU3 PU2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PD5 PD4 PD3 PD2
rw rw rw rw
RM0444
17 16
Res. Res.
1 0
PU1 PU0
rw rw
17 16
Res. Res.
1 0
PD1 PD0
rw rw