Ucpd Reset And Clocks; Table 232. Ucpd Internal Signals; Figure 404. Clock Division And Timing Elements - ST STM32G0 1 Series Reference Manual

RM0444
The following table lists key internal signals.
Internal signal name
ucpd_pclk
ucpd_ker_ck
ucpd_tx_dma
ucpd_rx_dma
ucpd_it
ucpd_wkup
clk_rq
38.4.2

UCPD reset and clocks

The peripheral has a single reset signal (APB bus reset).
The register section is clocked with the APB clock (ucpd_pclk).
The main functional part of the transmitter is clocked with ucpd_clk clock, pre-scaled from
the ucpd_ker_ck (HSI16) clock according to the PSC_USBPDCLK[2:0] bitfield of the
UCPD_CFGR1 register. The main functional part of the receiver is clocked with the
ucpd_rx_clk recovered from the incoming bitstream.
The receiver is designed to work in the clock frequency range from 6 to 18 MHz. However,
the optimum performance is ensured in the range from 9 to 18 MHz.
The following diagram shows the clocking and timing elements of the UCPD peripheral.
ucpd_ker_ck
ucpd_pclk
Refer to the USB PD specification in order to set appropriate delays. For tTransitionWindow
and especially for tInterFrameGap, the clock frequency uncertainty must be taken into
account so as to respect specified timings in all cases.
USB Type-C™ / USB Power Delivery interface (UCPD)

Table 232. UCPD internal signals

Signal type
Input
Input
Input/Output
Input/Output
Output
Output
Output

Figure 404. Clock division and timing elements

Pre-scaler ucpd_clk
/1 to /16
"Half bit" divider
PSC_USBPDCLK[2:0]
HBITCLKDIV[5:0]
Registers
RM0444 Rev 5
APB clock for registers
Rx DMA acknowledge / request
Tx DMA acknowledge / request
Interrupt request (all interrupts OR-ed) connected to NVIC
Wakeup request connected to EXTI
Clock request connected to RCC
Clock division
hbit_clk (~ 600 kHz)
/1 to /64
"tTransitionWindow"
TRANSWIN[4:0]
"tInterFrameGap"
IFRGAP[4:0]
Description
Kernel clock
Counters
2 to 32
2 to 32
BMC receiver
BMC transmitter
MSv45536V2
1311/1390
1346