Low-Power Features; Wait Mode Conversion - ST STM32G0 1 Series Reference Manual

Analog-to-digital converter (ADC)
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted and its partial result discarded
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
•
The DMA is stopped
DMA circular mode (DMACFG
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
15.6

Low-power features

15.6.1

Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only
if the previous data has been treated, once the ADC_DR register has been read or if the
EOC bit has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.
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