Figure 184. External Trigger Input Block - ST STM32G0 1 Series Reference Manual

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General-purpose timers (TIM2/TIM3/TIM4)

ETR0 input from AF controller

ETR1..15 inputs from

on-chip sources

For example, to configure the upcounter to count each 2 rising edges on ETR, use the

following procedure:

Select the proper ETR source (internal or external) with the ETRSEL[3:0] bits in the

TIMx_AF1 register.

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency

which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When

the ETRP signal is faster, the user should apply a division of the external signal by a proper

ETPS prescaler setting.

Figure 184. External trigger input block

/1, /2, /4, /8

RM0444 Rev 5

External clock

External clock

Internal clock

(internal clock)

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