Tim14 Interrupt Enable Register (Tim14_Dier); Tim14 Status Register (Tim14_Sr) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock and gated mode can work only if the CEN bit has been previously set by
24.4.2

TIM14 Interrupt enable register (TIM14_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:2
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
24.4.3

TIM14 status register (TIM14_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
0: Counter disabled
1: Counter enabled
software. However trigger mode can set the CEN bit automatically by hardware.
12 11 10 9
Res. Res. Res.
Reserved, must be kept at reset value.
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0: Update interrupt disabled
1: Update interrupt enabled
12 11 10 9
Res. Res. CC1OF
rc_w0
8 7 6
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0444 Rev 5
General-purpose timers (TIM14)
5 4 3 2
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
1 0
CC1IE UIE
rw rw
1 0
CC1IF UIF
rc_w0 rc_w0
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