Wwdg Configuration Register (Wwdg_Cfr) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
29.5.2

WWDG configuration register (WWDG_CFR)

Address offset: 0x004
Reset value: 0x0000 007F
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. WDGTB[2:0]
rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 13:11 WDGTB[2:0]: Timer base
Bit 9 EWI: Early wakeup interrupt
Bits 6:0 W[6:0]: 7-bit window value
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter, decremented every
[1:0]
WDGTB
(4096 x 2 ) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).
27 26 25
Res. Res. Res.
11 10 9
Res. EWI
rw rs
The timebase of the prescaler can be modified as follows:
000: CK Counter Clock (PCLK div 4096) div 1
001: CK Counter Clock (PCLK div 4096) div 2
010: CK Counter Clock (PCLK div 4096) div 4
011: CK Counter Clock (PCLK div 4096) div 8
100: CK Counter Clock (PCLK div 4096) div 16
101: CK Counter Clock (PCLK div 4096) div 32
110: CK Counter Clock (PCLK div 4096) div 64
111: CK Counter Clock (PCLK div 4096) div 128
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
These bits contain the window value to be compared with the down-counter.
System window watchdog (WWDG)
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res.
rw
RM0444 Rev 5
21 20 19 18
Res. Res. Res.
5 4 3 2
W[6:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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872