Figure 217. Counter Timing Diagram, Internal Clock Divided By N - ST STM32G0 1 Series Reference Manual

RM0444 Basic timers (TIM6/TIM7)

Figure 217. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
1F
Counter register 00
20
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31081V2
Figure 218. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload
FF 36
register
Write a new value in TIMx_ARR
MS31082V2
RM0444 Rev 5 707/1390
714