Syscfg Interrupt Line 10 Status Register (Syscfg_Itline10); Syscfg Interrupt Line 11 Status Register (Syscfg_Itline11) - ST STM32G0 1 Series Reference Manual

Table of Contents

System configuration controller (SYSCFG)

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DMA1_CH1: DMA1 channel 1 interrupt request pending

SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)

Address offset: 0xA8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DMA1_CH3: DMA1 channel 3 interrupt request pending

Bit 0 DMA1_CH2: DMA1 channel 2 interrupt request pending

Address offset: 0xAC

System reset value: 0x0000 0000

1. Only significant on devices integrating the corresponding DMA instance and channel, otherwise reserved. Refer to

Section 1.4: Availability of

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 DMA2_CH5: DMA2 channel 5 interrupt request pending

Bit 8 DMA2_CH4: DMA2 channel 4 interrupt request pending

Bit 7 DMA2_CH3: DMA2 channel 3 interrupt request pending

Bit 6 DMA2_CH2: DMA2 channel 2 interrupt request pending

Bit 5 DMA2_CH1: DMA2 channel 1 interrupt request pending

peripherals.

RM0444 Rev 5

Show Quick Links

Table of Contents

Do you have a question about the STM32G0 1 Series and is the answer not in the manual?