Table 228. Definition Of Allocated Buffer Memory - ST STM32G0 1 Series Reference Manual

RM0444
the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint/channel descriptor and it is normally defined during
the enumeration process according to its maxPacketSize parameter value (see "Universal
Serial Bus Specification").
31 30 29
BLSIZE NUM_BLOCK[4:0]
rw rw rw
15 14 13
rw rw rw
Bit 31 BLSIZE: Block size
Bits 30:26 NUM_BLOCK[4:0]: Number of blocks
Bits 25:16 COUNTn_RX[9:0]: Reception byte count
Bits 15:0 ADDRn_RX[15:0]: Reception buffer address
NUM_BLOCK[4:0]
Universal serial bus full-speed host/device interface (USB)
28 27 26 25
rw rw rw r
12 11 10 9
rw rw rw rw
This bit selects the size of memory block used to define the allocated buffer area.
– If BLSIZE = 0, the memory block is 2-byte large, which is the minimum block
allowed in a half-word wide memory. With this block size the allocated buffer size
ranges from 2 to 62 bytes.
– If BLSIZE = 1, the memory block is 32-byte large, which permits to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size theoretically ranges from 32 to 1024 bytes, which is the longest
packet size allowed by USB standard specifications. However, the applicable size is
limited by the available buffer memory.
These bits define the number of memory blocks allocated to this packet buffer. The actual
amount of allocated memory depends on the BLSIZE value as illustrated in
These bits contain the number of bytes received by the endpoint/channel associated with the
USB_CHEPnR register during the last OUT/SETUP transaction addressed to it.
These bits point to the starting address of the packet buffer, which contains the data received
by the endpoint/channel associated with the USB_CHEPnR register at the next OUT/SETUP
token addressed to it. Bits 1 and 0 must always be written as "00" since packet memory is
word wide and all packet buffers must be word aligned.

Table 228. Definition of allocated buffer memory

Value of
0 (00000)
1 (00001)
2 (00010)
3 (00011)
...
14 (01110)
15 (01111)
24 23 22
COUNTn_RX[9:0]
r r r
8 7 6
ADDRn_RX[15:0]
rw rw rw
Memory allocated
when BLSIZE=0
Not allowed
2 bytes
4 bytes
6 bytes
...
28 bytes
30 bytes
RM0444 Rev 5
21 20 19 18
r r r r
5 4 3 2
rw rw rw rw
Memory allocated
when BLSIZE=1
32 bytes
64 bytes
96 bytes
128 bytes
...
480 bytes
17 16
r r
1 0
rw rw
Table 228.
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