Bpu Functionality; Dwt (Data Watchpoint); Dwt Functionality; Dwt Program Counter Sample Register - ST STM32G0 1 Series Reference Manual

Debug support (DBG)
40.7.1

BPU functionality

The processor breakpoints implement PC based breakpoint functionality.
Refer the Armv6-M Arm and the Arm CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.
40.8

DWT (Data Watchpoint)

The Cortex
40.8.1

DWT functionality

The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the Armv6-M Arm.
40.8.2

DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the Armv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the Armv6-M Arm for more information.
The Cortex
those that fail.
40.9

MCU debug component (DBG)

The MCU debug component helps the debugger provide support for:
•
Low-power modes
•
Clock control for timers, watchdog and I2C during a breakpoint
40.9.1

Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
•
In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.
•
In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.
This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.
1372/1390
®
-M0+ DWT implementation provides two watchpoint register sets.
®
-M0+ DWT_PCSR records both instructions that pass their condition codes and
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