Clock Selection; Figure 246. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
Figure 246. Update rate examples depending on mode and TIMx_RCR register
25.4.4

Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
•
External clock mode1: external input pin
• Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, TIM1 can be configured to act as a prescaler for TIM15.
Refer to
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
752/1390
Counter
TIMx_CNT
TIMx_RCR = 0 UEV
TIMx_RCR = 1 UEV
TIMx_RCR = 2 UEV
TIMx_RCR = 3 UEV
TIMx_RCR = 3
and
re-synchronization UEV
UEV Update Event: preload registers transferred to active registers
and update interrupt generated.
Using one timer as prescaler for another timer on page 664
RM0444 Rev 5
settings
Edge-aligned mode
Upcounting
(by SW)
RM0444
MS31084V2
for more details.