Clocks - ST STM32G0 1 Series Reference Manual

RM0444
5.2

Clocks

The device provides the following clock sources producing primary clocks:
•
HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about
16 MHz)
•
HSI48 RC - a high-speed fully-integrated RC oscillator producing HSI48 clock for USB
(about 48 MHz)
•
HSE OSC - a high-speed oscillator with external crystal/ceramic resonator or external
clock source, producing HSE clock (4 to 48 MHz)
•
LSI RC - a low-speed fully-integrated RC oscillator producing LSI clock (about 32 kHz)
• LSE OSC - a low-speed oscillator with external crystal/ceramic resonator or external
clock source, producing LSE clock (accurate 32.768 kHz or external clock up to
1 MHz)
•
I2S_CKIN - pin for direct clock input for I2S1 peripheral
Each oscillator can be switched on or off independently when it is not used, to optimize
power consumption. Check sub-sections of this section for more functional details. For
electrical characteristics of the internal and external clock sources, refer to the device
datasheet.
The device produces secondary clocks by dividing or/and multiplying the primary clocks:
•
HSISYS - a clock derived from HSI16 through division by a factor programmable from 1
to 128
•
PLLPCLK, PLLQCLK and PLLRCLK - clocks output from the PLL block
•
SYSCLK - a clock obtained through selecting one of LSE, LSI, HSE, PLLRCLK, and
HSISYS clocks
•
HCLK - a clock derived from SYSCLK through division by a factor programmable from
1 to 512
• HCLK8 - a clock derived from HCLK through division by eight
•
PCLK - a clock derived from HCLK through division by a factor programmable from 1 to
16
•
TIMPCLK - a clock derived from PCLK, running at PCLK frequency if the APB
prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
•
LPTIMx_IN - clock from LPTIMx_INx pins, selectable for the LPTIM peripheral
More secondary clocks are generated by fixed division of HSE, HSI16 and HCLK clocks.
The HSISYS is used as system clock source after startup from reset, with the division by 1
(producing HSI16 frequency).
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains,
respectively. Their maximum allowed frequency is 64 MHz.
RM0444 Rev 5
Reset and clock control (RCC)
163/1390
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