Wwdg Status Register (Wwdg_Sr); Wwdg Register Map; Table 145. Wwdg Register Map And Reset Values - ST STM32G0 1 Series Reference Manual

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System window watchdog (WWDG)

WWDG status register (WWDG_SR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag

The following table gives the WWDG register map and reset values.

This bit is set by hardware when the counter has reached the value 0x40. It must be cleared

by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not

Section 2.2 on page 58

for the register boundary addresses.

RM0444 Rev 5

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