Tim14 Registers; Tim14 Control Register 1 (Tim14_Cr1) - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM14)
24.4

TIM14 registers

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
24.4.1

TIM14 control register 1 (TIM14_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
730/1390
12 11 10 9
UIFRE
Res. CKD[1:0]
MAP
rw rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
8 7 6
ARPE Res.
rw rw
RM0444 Rev 5
5 4 3 2
Res. Res. OPM URS
rw rw
RM0444
1 0
UDIS CEN
rw rw