Dac Channel2 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L2); Dac Channel2 8-Bit Right-Aligned Data Holding Register (Dac_Dhr8R2) - ST STM32G0 1 Series Reference Manual

Digital-to-analog converter (DAC)
16.7.7

DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)

This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
16.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
430/1390
27 26 25
Res. Res. Res.
11 10 9
DACC2DHR[11:0]
rw rw rw rw
These bits are written by software which specify 12-bit data for DAC channel2.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
These bits are written by software which specifies 8-bit data for DAC channel2.
24 23 22
Res. Res. Res. Res.
8 7 6
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res.
rw rw
RM0444 Rev 5
Section 16.3: DAC
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res.
rw rw
Section 16.3: DAC
21 20 19 18
Res. Res. Res.
5 4 3 2
DACC2DHR[7:0]
rw rw rw rw
RM0444
17 16
Res. Res.
1 0
Res. Res.
17 16
Res. Res.
1 0
rw rw