Table 127. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature - ST STM32G0 1 Series Reference Manual

RM0444

Table 127. Output control bits for complementary OCx and OCxN channels with break feature

Control bits
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state
1 X
0
0
1
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and AFIO registers.
X 0 0
0 0 1
0 1 0
X 1 1
1 0 1
1 1 0
X X
0 0
0 1
X
1 0
1 1
General-purpose timers (TIM15/TIM16/TIM17)
(TIM15)
Output Disabled (not driven by the timer: Hi-Z)
OCx=0
OCxN=0, OCxN_EN=0
Output Disabled (not driven
by the timer: Hi-Z)
OCx=0
OCxREF + Polarity
OCx=OCxREF XOR CCxP
OCREF + Polarity + dead-
time
Off-State (output enabled
with inactive state)
OCx=CCxP
OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1
Output disabled (not driven by the timer: Hi-Z)
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCxN=CCxNP
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
RM0444 Rev 5
(1)
Output states
OCxN output state
OCxREF + Polarity
OCxN=OCxREF XOR CCxNP
Output Disabled (not driven by
the timer: Hi-Z)
OCxN=0
Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxREF + Polarity
OCxN=OCxREF XOR CCxNP
Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1
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