Apb Peripheral Clock Enable In Sleep/Stop Mode Register 1; (Rcc_Apbsmenr1) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2SMEN: DMA2 and DMAMUX clock enable during Sleep mode
Bit 0 DMA1SMEN: DMA1 and DMAMUX clock enable during Sleep mode
5.4.19

APB peripheral clock enable in Sleep/Stop mode register 1

(RCC_APBSMENR1)

Address offset: 0x4C
Reset value: 0b1111 1111 1111 1111 1111 1111 1011 0111
31 30 29 28
DAC1
LPTIM
LPTIM PWR
SME
2
1SMEN SMEN
(1)
SMEN
N
rw rw rw rw
15 14 13 12
USB FDCA
SPI3
SME N
SPI2
SMEN
N SMEN
SMEN
(1)
(1) (1)
rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of
Bit 31 LPTIM1SMEN: Low Power Timer 1 clock enable during Sleep and Stop modes
Bit 30 LPTIM2SMEN: Low Power Timer 2 clock enable during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is
enabled to at least one DMA peripheral.
27 26 25
UCPD
2
UCPD1
DBG
(
(1)
SMEN SMEN
SMEN
1)
rw rw rw
11 10 9
USART6
RTC
WWDG
SMEN
APB
SMEN
(1)
SMEN
rw rw rw
peripherals.
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
24 23 22 21
I2C3
CEC
I2C2 I2C1
SMEN
(1)
SMEN SMEN
SMEN
(1)
rw rw rw rw
8 7 6 5
LP
UART
USART5 TIM7
2
SMEN SMEN
Res.
(
(1) (1)
SMEN
1)
rw rw rw
RM0444 Rev 5
Reset and clock control (RCC)
(1)
20 19 18
LP
USART4 USART3
UART USART2
SMEN SMEN
1
(1) (1)
SMEN
rw rw rw
4 3 2
TIM6 TIM4
SMEN SMEN
Res.
(1) (1)
rw rw
(1)
17 16
CRSS
(1
MEN
SMEN
)
rw rw
1 0
TIM3 TIM2
SMEN SMEN
rw rw
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