From Comp1, Comp2, And Comp3 To Tim1, Tim2, Tim3, Tim4, Tim15; Tim16, And Tim17; From System Errors To Tim1, Tim2, Tim3, Tim4, Tim15, Tim16; And Tim17 - ST STM32G0 1 Series Reference Manual

RM0444
More information is in:
•
Section 15.2: ADC main features
•
Section 15.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
•
Figure 15.9: Temperature sensor and internal reference voltage
•
Figure 15.10: Battery voltage monitoring
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.9

From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15,

TIM16, and TIM17

Purpose
COMP1, COMP2, and COMP3 comparator outputs can be connected to input capture or
TIMx_ETR inputs of TIM1, TIM2, TIM3, or TIM4.
The connection to ETR is described in
COMP1, COMP2, and COMP3 comparator outputs can also act as TIMx_BKIN or
TIMx_BKIN2 break input signals for TIM1, TIM15, TIM16, and TIM17, through selecting
GPIO alternate function using open drain connection of I/O. See
Bidirectional break
The possible connections are given in:
•
Section 21.4.23: TIM1 option register 1 (TIM1_OR1)
•
Section 21.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
•
Section 22.4.22: TIM2 option register 1 (TIM2_OR1)
•
Section 25.3: TIM16/TIM17 main features
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.10

From system errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16,

and TIM17

Purpose
CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can
generate system errors in the form of timer break toward TIM1, TIM2, TIM3, TIM4, TIM15,
TIM16, and TIM17.
The purpose of the break function is to protect power switches driven by PWM signals from
the timers.
Section 21.3.4: External trigger
inputs.
RM0444 Rev 5
Interconnect matrix
input.
Section 21.3.17:
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