Standby Mode - ST STM32G0 1 Series Reference Manual

RM0444
4.3.8

Standby mode

The Standby mode allows to achieve the lowest power consumption with BOR. It is based
on the Cortex
SRAM content is preserved). The PLL, the HSI16 and the HSE oscillators are also switched
off.
The content of the registers is lost except for the registers in the RTC domain and Standby
circuitry (see
PWR_CR3 register. In this case the low-power regulator is on and provides the supply to the
SRAM only.
The BOR is available in Standby mode.
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ENB_ULP bit of the PWR_CR3 register allows to decrease the
current consumption in this mode, but any drop of the voltage below the operating
conditions between two active periods of the supply detector results in a non-generation of
PDR reset.
I/O states in Standby mode
In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x=A, B, C, D, F), or with a pull-down (refer to PWR_PDCRx registers (x=A, B, C,
D, F)), or can be kept in analog mode.
The RTC outputs on PC13 and PA4 are functional in Standby mode. PC14 and PC15 used
for LSE are also functional. Five wakeup pins (WKUPx, x=1,2,4,5,6) and the two tampers
are available.
Entering Standby mode
The MCU enters Standby mode according to
SLEEPDEEP bit in the Cortex
Refer to
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 28.3: IWDG functional
•
Real-time clock (RTC) and tamper (TAMP): this is configured by the RTCEN bit in the
RTC domain control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC
domain control register (RCC_BDCR)
®
-M0+ deepsleep mode, with the voltage regulators disabled (except when the
Figure 5). The SRAM content is lost except if the RRS bit is set in the
®
Table 32: Standby mode summary
Entering low-power
-M0+ System Control register is set.
for details on how to enter Standby mode.
description.
RM0444 Rev 5
Power control (PWR)
modes, when the
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