Fdcan Tx Buffer Request Pending Register (Fdcan_Txbrp) - ST STM32G0 1 Series Reference Manual

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FD controller area network (FDCAN)

FDCAN Tx buffer request pending register (FDCAN_TXBRP)

Address offset: 0x00C8

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 TRP[2:0]: Transmission request pending

Each Tx Buffer has its own transmission request pending bit. The bits are set via register

TXBAR. The bits are reset after a requested transmission has completed or has been

canceled via register TXBCR.

After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with

the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register

TXBRP. In case a transmission has already been started when a cancellation is requested,

this is done at the end of the transmission, regardless whether the transmission was

successful or not. The cancellation request bits are reset directly after the corresponding

TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signaled via TXBCF

after successful transmission together with the corresponding TXBTO bit

when the transmission has not yet been started at the point of cancellation

when the transmission has been aborted due to lost arbitration

when an error occurred during frame transmission

In DAR mode all transmissions are automatically canceled if they are not successful. The

corresponding TXBCF bit is set for all unsuccessful transmissions.

0: No transmission request pending

1: Transmission request pending

TXBRP bits set while a Tx scan is in progress are not considered during this particular Tx

scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is canceled

immediately, the corresponding TXBRP bit is reset.

RM0444 Rev 5

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