Hdmi-Cec Interrupts; Table 245. Hdmi-Cec Interrupts - ST STM32G0 1 Series Reference Manual

HDMI-CEC controller (CEC)
Time
T
6
39.6

HDMI-CEC interrupts

An interrupt can be produced:
•
during reception if a receive block transfer is finished or if a receive error occurs.
• during transmission if a transmit block transfer is finished or if a transmit error occurs.
Rx-byte received
End of reception
Rx-overrun
Rxbit rising error
Rx-short bit period error
Rx-long bit period error
Rx-missing acknowledge error
Arbitration lost
Tx-byte request
End of transmission
Tx-buffer underrun
Tx-error
Tx-missing acknowledge error
1356/1390
Table 244. TXERR timing parameters (continued)
RXTOL ms
0 2.75
1 2.95

Table 245. HDMI-CEC interrupts

Interrupt event
RM0444 Rev 5
Description
The latest time for the start of a following bit.
Event flag
RXBR
RXEND
RXOVR
BRE
SBPE
LBPE
RXACKE
ARBLST
TXBR
TXEND
TXUDR
TXERR
TXACKE
RM0444
Enable control bit
RXBRIE
RXENDIE
RXOVRIE
BREIE
SBPEIE
LBPEIE
RXACKEIE
ARBLSTIE
TXBRIE
TXENDIE
TXUDRIE
TXERRIE
TXACKEIE