Tim14 Timer Input Selection Register (Tim14_Tisel); Tim14 Register Map; Table 124. Tim14 Register Map And Reset Values - ST STM32G0 1 Series Reference Manual

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Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

TIM14 timer input selection register (TIM14_TISEL)

Address offset: 0x68

Reset value: 0x0000

Bits 15:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input

1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.

TIMx registers are mapped as 16-bit addressable registers as described in the tables below:

If channel CC1 is configured as output:

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when

an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

0000: TIM14_CH1 input

0001: RTC CLK

0010: HSE/32

Others: Reserved

RM0444 Rev 5

General-purpose timers (TIM14)

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